Add wolfBoot port for STM32N6 (NUCLEO-N657X0-Q) by aidangarske · Pull Request #720 · wolfSSL/wolfBoot

aidangarske · 2026-03-11T01:17:33Z

Summary

Add TrustZone (TZEN=1) support for the STM32N6 port with proper secure/non-secure SAU configuration, firmware update swap support, and an enhanced test application with UART output.

Features

TrustZone support (TZEN=1): wolfBoot runs from secure SRAM (0x24000000) using secure peripheral aliases. SAU configured with proper secure/non-secure regions. Application boots into non-secure state.
Non-TrustZone mode (TZEN=0): wolfBoot runs from non-secure SRAM (0x34000000) with blanket SAU NSC region for full memory access.
Firmware update (A/B swap): Full sector-by-sector swap working with PART_BOOT_EXT to handle shared XSPI2 NOR flash between boot and update partitions.
Enhanced test application: UART output with firmware version, partition state, boot status, and automatic wolfBoot_success() handling for TESTING state. LED indicates firmware version (blue=v1, red=v2+).
New config: config/examples/stm32n6-tz.config for TrustZone-enabled builds.
CI: Added stm32n6 and stm32n6-tz build tests to test-configs.yml.
Flash script: --test-update mode now writes update trigger magic (pBOOT) and auto-detects TZEN for correct SRAM load address.

Fixes

UART clock: Corrected PCLK2 frequency from 300 MHz to 200 MHz (IC2=400 MHz / AHB prescaler 2).
uart_write linkage: Removed static qualifier and fixed signature to match printf.h (unsigned int len).
SAU configuration: Added SAU init to hal_init() — without it, the IDAU blocks secure CPU access to XSPI2 memory-mapped region (0x70000000), causing bus faults during image verification.
Shared flash (PART_BOOT_EXT): Boot and update partitions share the same XSPI2 NOR flash. Without PART_BOOT_EXT, the update swap reads boot partition data via XIP while XSPI2 is in SPI command mode, causing bus faults. The ext_flash_* functions now translate absolute memory-mapped addresses to device-relative offsets.
XIP write buffer: nor_flash_write() copies source data to a stack buffer before issuing SPI commands, since the source pointer may reference XIP flash that becomes inaccessible when XSPI2 leaves memory-mapped mode.
dcache ordering: Moved dcache_enable() after octospi_init() to prevent caching stale data from the flash region before memory-mapped mode is configured.
Boot path for Cortex-M55: Excluded STM32N6 from blxns non-secure boot path and non-secure VTOR, since the CPU security state depends on the SRAM alias used (IDAU-based), not a runtime TrustZone transition.
OpenOCD: Requires upstream openocd-org/openocd (not ST fork) for target/stm32n6x.cfg support.

Test Results (NUCLEO-N657X0-Q hardware)

Test	TZEN=0	TZEN=1
Build	Pass	Pass
Basic boot (v1)	Pass	Pass
UART output	Pass	Pass
Firmware update swap (v1→v2)	Pass	Pass
Test-app auto-success	Pass	Pass
TrustZone state	Off	Secure

Boot from cold power on

dgarske

Great work! I haven't tested on hardware yet, but have looked over each line.

Add HAL, build system, test app, and documentation for the STM32N6 (Cortex-M55) targeting the NUCLEO-N657X0-Q board. wolfBoot runs from SRAM as FSBL and boots a signed application via XIP from external NOR flash on XSPI2.

Fix PLL1 bypass bit (PLL1BYP) in PLL1CFGR1 that Boot ROM leaves set, which was routing HSI 64 MHz directly to PLL output instead of the 1200 MHz VCO. CPU now runs at 600 MHz (verified via DWT CYCCNT). - Clear PLL1CFGR1 BYP bit to enable VCO output - Simplify PLL1CFGR3 configuration to single write - Consolidate flash write/erase into shared nor_flash_write/erase helpers - Rename xspi_ functions to octospi_ for consistency with register macros - Add CORTEX_M55 define to arch.mk for future use - Add clock tree documentation in clock_config() and PWR_VOSCR - Combine CPUSW and SYSSW clock switch into single register write - Add XSPI2 RAMFUNCTION comments and TEF error handling - Add release announcement doc (docs/release-stm32n6.md) - wolfBoot binary: 23KB, test-app: 3KB

Copilot

Copilot was unable to review this pull request because the user who requested the review has reached their quota limit.

- Fix UART: remove static from uart_write, fix signature to match printf.h, correct PCLK2 clock frequency (200 MHz not 300 MHz) - Add SAU configuration: blanket NSC region for non-TZ, proper secure/non-secure SAU regions for TZEN=1 - Add PART_BOOT_EXT support: boot and update partitions share the same XSPI2 NOR flash, ext_flash_addr() translates absolute memory-mapped addresses to device-relative offsets - Buffer XIP data in nor_flash_write() before SPI commands - Move dcache_enable() after octospi_init() to prevent stale reads - Add TZ_SECURE() macro with conditional secure/non-secure peripheral base addresses in hal/stm32n6.h - Add TZEN=1 support: wolfBoot runs from secure SRAM (0x24000000), app boots into non-secure state, flash script auto-detects TZEN - Exclude STM32N6 from stm32_tz.o (uses its own SAU config) and from blxns boot path (CORTEX_M55 uses regular boot) - Enhanced test-app with UART output, partition info, version display, state handling, and auto-success for TESTING state - Add stm32n6-tz.config example and CI entries in test-configs.yml - Update Targets.md with TrustZone, SAU, PART_BOOT_EXT, and UART clock documentation - Add DEBUG_UART=1 and RAM_CODE=1 to stm32n6.config

…ing code was only loading to SRAM)

dgarske

This PR is in good shape, but the boot ROM from QSPI isn't working. @aidangarske please work on it. Not rush on this, it can be post release. I think it does require some OTP registers to be set, but I tried setting OTA124 and it didn't change the results. Note you also have to set BOOT0/BOOT1 jumpers to switch between boot modes.

aidangarske

Skoll Code Review

Scan type: review-security
Overall recommendation: COMMENT
Findings: 5 total — 4 posted, 1 skipped
4 finding(s) posted as inline comments (see file-level comments below)

Posted findings

[Medium] TZEN=1 boot path sets secure VTOR to non-secure application memory — src/boot_arm.c:422-466
[Medium] octospi_write_enable ignores return value allowing silent flash operation failures — hal/stm32n6.c:143-147
[Low] Flash script uses predictable temporary file path — tools/scripts/stm32n6_flash.sh:142
[Info] Documentation describes TZEN=1 secure SRAM alias but code uses non-secure alias for both modes — docs/Targets.md:1855-1860

Skipped findings

[Low] ~~Unaligned uint32_t pointer dereference in octospi_cmd data transfer loop~~

Review generated by Skoll

dgarske · 2026-05-04T21:52:25Z

@aidangarske how's this going? If you won't have time in the next week let me know and I can finish it up.

aidangarske self-assigned this Mar 11, 2026

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aidangarske force-pushed the stm32n6-port-wolfboot branch from fedaf00 to 1416f2f Compare March 11, 2026 18:37

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aidangarske requested review from danielinux and dgarske March 11, 2026 18:58

aidangarske marked this pull request as ready for review March 11, 2026 18:58

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Comment thread Makefile

dgarske assigned dgarske and wolfSSL-Bot and unassigned aidangarske Mar 16, 2026

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aidangarske added 2 commits March 18, 2026 12:43

Add wolfBoot port for STM32N6 (NUCLEO-N657X0-Q)

23f73f1

Add HAL, build system, test app, and documentation for the STM32N6 (Cortex-M55) targeting the NUCLEO-N657X0-Q board. wolfBoot runs from SRAM as FSBL and boots a signed application via XIP from external NOR flash on XSPI2.

dgarske previously approved these changes Mar 18, 2026

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dgarske assigned danielinux and unassigned dgarske Mar 18, 2026

Copilot AI review requested due to automatic review settings March 18, 2026 19:54

dgarske dismissed their stale review via cc789ae March 18, 2026 19:54

dgarske force-pushed the stm32n6-port-wolfboot branch from 4100805 to cc789ae Compare March 18, 2026 19:54

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dgarske assigned dgarske and unassigned danielinux Mar 18, 2026

dgarske force-pushed the stm32n6-port-wolfboot branch from cc789ae to 896c2a7 Compare March 18, 2026 20:14

Fixes to support botting image on QSPI NOR flash from boot ROM (exist…

6585a0b

…ing code was only loading to SRAM)

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dgarske unassigned wolfSSL-Bot Mar 19, 2026

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aidangarske commented Apr 14, 2026

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Comment thread src/boot_arm.c

Comment thread hal/stm32n6.c

Comment thread tools/scripts/stm32n6_flash.sh

Comment thread docs/Targets.md

dgarske self-requested a review April 15, 2026 22:15

dgarske added the Later It won't be fixed in the upcoming release label Apr 15, 2026

dgarske assigned aidangarske and unassigned aidangarske May 4, 2026

dgarske self-assigned this May 4, 2026

danielinux removed the Later It won't be fixed in the upcoming release label May 7, 2026

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Summary

Features

Fixes

Test Results (NUCLEO-N657X0-Q hardware)

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Skoll Code Review

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aidangarske commented Mar 11, 2026 •

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